1. Field of the Invention
The present invention is directed generally to semiconductors and more specifically to a method for manufacturing a trench in a substrate for use in smart-power technology.
2. Description of the Related Art
For various applications, it is necessary to manufacture trenches having a high aspect ratio (aspect ratio is the quotient of trench depth to trench width) in substrates that comprise a first silicon layer at least at the surface, an insulating layer therebelow, and a second silicon layer below the latter. The trenches should thereby extend through the first silicon layer and through the insulating layer down to the second silicon layer.
For example, such trenches are required for contacting circuit elements in three-dimensional circuits that are realized in silicon layers arranged above one another but respectively separated by insulating layers.
A further use of such trenches occurs in smart-power technology on SOI substrates. In smart-power technology, complex logic components are monolithically integrated in one substrate with high-voltage power components. Since the logic components are operated with voltage levels of around 5 volts but voltages up to 500 volts occur at the high-voltage power components, an electrical separation of the high-voltage components from the logic components is required.
It is known (see, for example Yu Ohata et al, IEEE CICC, pages 443-446; A. Nakagawa et al, ISPS 1990, pages 97-101) to completely electrically insulate the high-voltage and low-voltage components from one another by dielectric insulation. To that end, the components are in a SOI substrate. An SOI substrate has an insulating layer of SiO.sub.2 on a monocrystalline wafer and a monocrystalline silicon layer on the insulating layer. This monocrystalline silicon layer is the surface of the SOI substrate. The components are in the monocrystalline layer. The insulating layer of the SOI substrate produces the vertical insulation, whereas the lateral insulation of the components is realized by trenches filled with insulating material. These trenches extend down to the surface of the insulating layer. They completely surround the component to be insulated in the monocrystalline silicon layer. For filling the trenches, for example, the sidewall is thermally oxidized, the remaining interspace is filled with polysilicon, is etched back and, subsequently, is oxidized at the surface. The trench filling is then has a polysilicon core that is completely enclosed by silicon oxide.
The trench is produced by using a trench mask that is predominantly SiO.sub.2. When the trench is to be etched through the insulating layer down to the surface of the monocrystalline silicon wafer, which represents the second silicon layer in this case for example, to produce a contact to the monocrystalline silicon wafer, the trench mask is also attacked in this etching. When the thickness of the trench mask is comparable to or less than that of the insulating layer, then the surface of the silicon layer in which the active components are integrated is incipiently etched and damaged in this etching.